1. Field of the Invention
This invention relates generally to the field of computer processors. More particularly, the invention relates to an apparatus and method for implementing a heterogeneous memory subsystem.
2. Description of the Related Art
Recent technology advancements allow for the integration of large memory structures on-die or as a die-stacked dynamic random access memory (DRAM). Such structures are much faster to access than off-die memory. Prior work has investigated using these large structures as a cache, or as part of a heterogeneous memory system, sometimes referred to as a non-uniform memory architecture (NUMA), under management of the operating system (OS).
Using this memory as a cache would waste a significant fraction of total memory space, especially for mobile systems where stacked memory may be as large as off-die memory. An OS-managed NUMA system, on the other hand, requires usage monitoring hardware to migrate frequently-used pages, and is often unable to capture pages that are highly utilized for short periods of time.